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e c 9223 multi - channel tft lcd supply e-cmos corp. (www.ecmos.com.tw) 5 e26 n - rev. f001 1/13 general description theEC9223 is an integrated power supply solution op timized for small to medium size thin- film transis tor (tft) liquid crystal displays (lcds). the boost converte r operates at a fixed frequency of 1.2mhz. the integrated n- channel fet has a current limit of 1.8a. the positi ve and negative charge pumps provide regulated tft lcd gate-on and gate-off supplies. both outputs can be adjusted by external resistive voltage dividers. the integrated operational amplifier is typically u sed for lcd vcom driving; the output can sink or so urce up to 150ma short-circuit current. a built-in voltage det ector generates a reset signal when the input volta ge drops below 2.6v. the reset signal is active low and has a 123ms blanking time during power-on. the EC9223 i s available in a thin 16-pin 3x3 mm wqfn green packag e. features qfn-16 pin configuration 2.5v to 5.5v input supply active-high enable control current-mode boost regulator - 1.2mhz switching frequency - integrated 20v/1.8a 700m fet - fast transient response to pulsed load - high efficiency up to 90% - adjustable high-accuracy output voltage(1% ) vgh positive charge pump vgl negative charge pump integrated unity-gain v com buffer - 150ma output current limit - 12v/us slew rate - 12mhz bandwidth low-voltage detection circuit soft-start and timed delay fault latch for all out puts thermal shutdown thin 3x3 mm 16-lead wqfn package applications tft lcd for notebooks tablet personal computer display car navigation display portable equipment
e c 9223 multi - channel tft lcd supply e-cmos corp. (www.ecmos.com.tw) 5 e26 n - rev. f001 2/13 pin description number name pin description 1 drvn negative charge pump driver output. 2 ref reference output. all power outputs are disabled u ntil ref exceeds its uvlo threshold. 3 agnd analog ground. 4 rstnn voltage detector output. rstnn is an active-low op en-drain output. 5 en enable control input pin. this pin has a 4ua pull- down current source. 6 opai unity-gain buffer input pin. 7 opao unity-gain buffer output pin. 8 avdd charge pump and unity-gain buffer supply. 9 pgnd boost converter power ground (source of the intern al nmos switch). 10 lx boost converter switching node (drain of the inter nal nmos switch). 11 vin supply for pwm, reference and other circuits. 12 fb boost converter feedback voltage input. 13 comp boost converter error amplifier compensation node. 14 fbp positive charge pump feedback input. 15 drvp positive charge pump driver output. 16 fbn negative charge pump feedback input. - tp thermal pad, connect to agnd. ordering information EC9223 nn xx x part number package marking marking information EC9223nnq1r wqfn 16l 9223 lllll 1. lllll lot no q1:wqfn r:tape & reel
e c 9223 multi - channel tft lcd supply e-cmos corp. (www.ecmos.com.tw) 5 e26 n - rev. f001 3/13 function block diagram
e c 9223 multi - channel tft lcd supply e-cmos corp. (www.ecmos.com.tw) 5 e26 n - rev. f001 4/13 typical application diagram
e c 9223 multi - channel tft lcd supply e-cmos corp. (www.ecmos.com.tw) 5 e26 n - rev. f001 5/13 package thermal resistance, ja power rating (t a < 25 c ) power rating (25 < t a < 85 c ) power rating (t a = 85c ) 16-ld qfn 103c /w 1.25w (125 - t a ) / 103 w 0.39w absolute maximum ratings note1: all voltages are referenced to ground with p gnd and agnd pins grounded. note2: absolute maximum ratings indicate limits b eyond which permanent damage to the device may occur. these are stress ratings only, and funct ional operation of the device at these or any other conditions beyond those indicated under "recommende d operating conditions" is not implied. for guaranteed specifications and test conditions, see the electrical specifications. recommended operation conditions power dissipation ratings input supply voltage, vin -0.3v to 6.5v voltages on en, rstnn -0.3v to 6.5v voltages on avdd, lx -0.3v to 22v voltages on fb, fbp, fbn, comp, ref -0.3v to (vin+0.3v) voltages on drvp, drvn, opai, opao -0.3v to (avdd+0.3v) storage temperature range -65c to 150c lead temperature (soldering, 10s maximum) 260c esd, human body mode 2kv esd, machine mode 200v junction temperature range -40c to 125c ambient temperature range -40c to 85c
e c 9223 multi - channel tft lcd supply e-cmos corp. (www.ecmos.com.tw) 5 e26 n - rev. f001 6/13 electrical specifications (v in =3.3v, av dd = 8.5v, t a =25c, unless otherwise specified) parameter symbol test conditions min typ max units system supply input supply voltage v in 2.5 -- 5.5 v vin under voltage lockout threshold v uvlo v in rising 1.8 2.0 2.2 v vin under voltage lockout threshold v uvlo hysteresis -- 0.1 -- v vin quiescent current i q v fb = 1.35v, lx no switching -- 0.3 -- ma vin quiescent current i q v fb = 1.15v, lx switching -- 0.8 -- ma en threshold v ih 2 -- -- en threshold v il -- -- 0.8 v thermal shutdown t shdn -- 150 -- main boost regulator fb regulation voltage v fb 1.188 1.2 1.212 v fb fault trip level falling edge 0.95 v fb load regulation 0< i load < full -1 % fb line regulation v in = 2.5 to 5.5v 0.15 0.25 %/v fb input bias current v fb = 1.25v -40 0 40 na fb transconductance g m ? i=5ua at comp, fb = comp 70 ua/v fb voltage gain a v fb to comp 1500 v/v lx current limit v fb =1.1v, duty cycle = 75% 1.4 1.8 2.2 a lx on-resistance r ds_lx i lx = 200ma 0.7 lx leakage current v lx = 19v, t a = +25c 0.1 10 ua current-sense transresistance 0.35 v/a maximum duty cycle duty 85 90 94 % soft-start period t ss1 7 ms reference ref output voltage v ref i ref =50ua 1.176 1.20 1.224 v ref load regulation i ref 0 e c 9223 multi - channel tft lcd supply e-cmos corp. (www.ecmos.com.tw) 5 e26 n - rev. f001 7/13 positive charge-pump regulator avdd supply range v avdd 6 16 v operating frequency f osc_cp 600 khz fbp regulation voltage v fbp 1.176 1.2 1.224 v fbp input bias current i fbp_bias v fbp =1.5v, t a = +25c -40 - 40 na drvp p-ch on-resistance r drvpp 20 drvp n-ch on-resistance r drvpn v avdd =10v,i drvp =20ma 20 fbp fault trip level falling edge 0.95 v soft-start period t ss2 5 ms negative charge-pump regulator avdd supply range v avdd 6 16 v operating frequency f osc_cp 600 khz fbn regulation voltage v fbn 210 240 270 mv fbn input bias current i fbn_bias v fbn = 0v, t a = +25c -40 - 40 na drvn p-ch on-resistance r drvnp 20 drvn n-ch on-resistance r drvnn v avdd =10v,i drvn =20ma 20 fbn fault trip level rising edge 0.45 v soft-start period t ss3 5 ms operational amplifier avdd supply range v avdd 6 16 v avdd supply current i avdd v opai = v avdd /2, no load 0.6 1.2 ma input offset voltage v os v opai =v avdd /2, t a = +25c -15 0 15 mv input bias current i bias v opai =v avdd /2, t a = +25c -100 100 na input common-mode voltage range 0 vavdd v opao i out = 100 a v avdd - 20 v avdd - 5 mv output-voltage-swing high voh opao i out = 5 ma v avdd - 200 v avdd - 150 mv opao i out = -100 a 5 20 mv output-voltage-swing low vol opao i out = -5 ma 150 200 mv slew rate sr v opao 20% to 80% with cl=10pf, rl=10k 8 12 v/us -3db bandwidth bw cl=10pf, rl=10k 12 mhz v opai =v avdd /2 , short output to gnd (sourcing) 100 150 ma short-circuit current iscc v opai =v avdd /2 , short output to avdd (sinking) 100 150 ma
e c 9223 multi - channel tft lcd supply e-cmos corp. (www.ecmos.com.tw) 5 e26 n - rev. f001 8/13 low-voltage detector v rst_th falling edge at v in 2.6 v reset threshold v rst_hyst 100 mv rstnn output voltage v rst i sink = 1ma 0.4 v reset blanking time t blk 120 ms application information the EC9223 offers an all-in-one solution for tft lc d. the chip includes a high-efficiency boost conver ter with a 20v/1.8a on-chip n-channel transistor for biasing o f the lcd, a regulated positive charge pump, a regu lated negative charge pump, and a unity-gain vcom buffer. a voltage detector circuit generates a reset signa l when the input voltage falls below 2.6v. tft lcd boost converter (avdd) the lcd panel avdd supply is generated from a high- efficiency pwm boost converter operating with curre nt mode control, and the switching frequency is 1.2mhz . during the on-period, ton, the synchronous fet connects one end of the inductor to ground, therefo re increasing the inductor current. after the fet t urns off, the inductor switching node, lx, is charged to a positi ve voltage by the inductor current. the freewheelin g diode turns on and the inductor current flows to the outp ut capacitor. the converter operates in the continu ous conduction mode (ccm) when the average input curren t iin is at least one-half of the inductor peak- to -peak ripple current, i lpp . the output voltage, avdd, is determined by the duty cycle, d, of the power fet on-time and the input v oltage, v in . the average load current, i load , can be calculated from the power conservation law . h v in i in = avdd i load where is the power conversion efficiency. for a lower lo ad current, the inductor current would decay to zer o during the free- wheeling period and the output node would be discon nected from the inductor for the remaining portion of the switching period. the converter would operate in the disconti nuous conduction mode (dcm). current mode control i s well known for its robustness and fast transient response. an inner cur rent feedback loop sets the on-time and the duty cy cle such that the current through the inductor equals to the current computed by the compensator. this loop acts within one switching cycle. a slope compensation ramp is added to suppress sub-ha rmonic oscillations. an outer voltage feedback loop subtracts the voltage on the fb pin from the internal reference vo ltage and feeds the difference to the compensator o perational transconductance (gm) amplifier. this amplifier is compensated by an external r-c network to allow the user to optimize the transient response and loop stability for the speci fic application conditions.
e c 9223 multi - channel tft lcd supply e-cmos corp. (www.ecmos.com.tw) 5 e26 n - rev. f001 9/13 compensation this current mode boost converter has a current sen se loop and a voltage feedback loop. the current se nse loop does not need any compensation. the voltage fe edback loop is compensated by an external series r- c network r comp and c comp from comp pin to ground. r comp sets the high-frequency loop gain and the unity gain bandwidth of the loop which determines t he transient response. c comp together with r comp determine the phase margin which relates to loop stability. output capacitor selection the output voltage ripple due to converter switchin g is determined by the output capacitor total capac itance, c out , and the output capacitor total effective series r esistance, esr. the first ripple component can be reduced by increasing c out . changing c out may require adjustment of compensation r and c in order to provide adequate phase margin and loop bandwidth. the second ripple component can be reduced by selec ting low-esr ceramic capacitors and using several smaller capacitors in parallel instead of just one large capacitor. inductor selection to prevent magnetic saturation of the inductor core the inductor has to be rated for a maximum current larger than i pk in a given application. since the chip provides cu rrent limit protection of 1.8a (typ) it is generall y recommended that the inductor be rated at least for 1.8a. selection of the inductor requires trade-off between the physical size (footprint x height) and its elec trical properties (current rating, inductance, resi stance). within a given footprint and height, an inductor with larger inductance typically comes with lower current rati ng and often larger series resistance. larger inductance typical ly requires more turns on the winding, a smaller co re gap or a core material with a larger relative permeability. an inductor with a larger physical size has better electrical properties than a smaller inductor. it is desirable to reduce the ripple current ilpp in order to reduce voltage noise on the input and output capacitors. in practice, the inductor is often much larger than the capacitors and it is easier and ch eaper to increase the size of the capacitors. the ripple cur rent ilpp is then chosen the largest possible while at t he same time not degrading the maximum input and outpu t current that the converter can operate with befor e reaching the current limit of the chip or the rated current of the inductor. for example, i lpp could be set to 20% of i max .
e c 9223 multi - channel tft lcd supply e-cmos corp. (www.ecmos.com.tw) 5 e26 n - rev. f001 10/13 positive charge pump (vgh) the positive charge pump is used to generate the tf t lcd gate on voltage. the output voltage, vgh, can be set by an external resistive divider. voltage v fbp is 1.2v. a single stage charge pump can produce an output voltage less than approximately twice the charge pump input voltage avd d. the output voltage vgh is regulated as the follow ing equation. the negative charge pump is used to generate the tf t lcd gate off voltage. the output voltage, vgl, is set with an external resistive divider from its output to ref with the midpoint connected to fbn. the erro r amplifier compares the feedback signal from fbn with an inter nal reference 240mv. the output voltage vgl is regu lated as the following equation. v ref is 1.2v. vcom buffer the v com buffer generates the bias supply for the back plan e of an lcd screen which is capacitively coupled to the pixel drive voltage. the purpose of the v com buffer is to hold the bias voltage steady while pi xel voltage changes dynamically. the buffer is designed to sust ain up to 75ma of output current. in transients, i t can deliver up to 150ma at which point the over current protection circuit limits the output current. exce ssive current draw over a period of time may cause the chip tempe rature to rise and set off the over temperature pro tection circuit.
e c 9223 multi - channel tft lcd supply e-cmos corp. (www.ecmos.com.tw) 5 e26 n - rev. f001 11/13 under voltage protection during normal operation (after completing the soft start sequence) EC9223 constantly monitors feedback pins fb, fbp and fbn. a fault condition occurs if fb falls below 0.95v o r fbp falls below 0.95v or fbn rises above 0.45v. if an y of the fault conditions persist for longer than 100ms, the chip sets a fault latch and shuts down. to turn the powe r supplies back on requires cycling of vin supply below the uvlo level o r toggling the en pin low and high. this will clear the fault latch and restore normal operation. over current protection the EC9223 has over-current protection (ocp) that l imits the peak inductor current in every switching cycle. it prevents large current from damaging the inductor a nd diode. once the inductor current exceeds the cur rent limit, the internal switch turns off immediately and short ens the duty cycle. the output voltage drops if the over-current condition occurs. current limit is affected by the input voltage, duty cycle, and inductor value. thermal-overload protection the EC9223 boost converter provides thermal-overloa d protection to prevents excessive power dissipatio n from overheating the ic. when the junction temperat ure exceeds t j = 150c, a thermal sensor activates the fault protection, which shuts down all outputs. to resume normal operation the chip internal temperatu re must drop at least by 15c. in addition, either the inpu t supply must be cycled below the uvlo level or the en pin must be toggled low and high to clear the fault lat ch. voltage detector circuit the internal voltage detector circuit monitors the chip input voltage v in . the chip can either drive rstnn pin low or leave it floating. while floating, rstnn is pull ed high by an external pull up resistor. when vin d rops below 2.6v the chip pulls rstnn pin low. in order to rele ase rstnn the v in voltage must rise above 2.7v. the voltage detector circuit is disabled and rstnn is floating while the chip is disabled and for 123ms from the t ime the chip is enabled (v in >uvlo and en is high). start-up and power-off control the EC9223 employs en pin to control the whole chip . pulling en high enables this device. when en goes high, once reference voltage is ready, the boost converto r starts operating. to limit the supply inrush curr ent during start up conditions, an internal soft-start circuitry is implemented. the soft-start circuitry will slowl y ramp up the output voltage during soft-start period, the soft-s tart period is 7ms for avdd and 5ms for vgh and vgl . the EC9223 shuts down to reduce the supply current when en is low. in this mode, all the internal blocks t urn off, and the n-channel mosfet is turned off as well. the boost convertors output is connected to vin by th e external inductor and rectifier diode.
e c 9223 multi - channel tft lcd supply e-cmos corp. (www.ecmos.com.tw) 5 e26 n - rev. f001 12/13 startup sequence
e c 9223 multi - channel tft lcd supply e-cmos corp. (www.ecmos.com.tw) 5 e26 n - rev. f001 13/13 package information (wqfn-16 3x3 mm)

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